module regfile(
  input           i_clk,

  input   [ 4:0]  i_mode,

  input   [ 3:0]  i_rn_sel,
  input   [ 3:0]  i_rm_sel,
  input   [ 3:0]  i_rs_sel,
  input   [ 3:0]  i_rd_sel,
  input           i_rd_sel_usr,

  output  [31:0]  o_rn,
  output  [31:0]  o_rm,
  output  [31:0]  o_rs,
  output  [31:0]  o_rd,

  input           i_we0,
  input   [ 3:0]  i_wa0,
  input           i_wa0_exc,
  input   [ 4:0]  i_wa0_mode_exc,
  input   [31:0]  i_d0,
  input           i_we1,
  input   [ 3:0]  i_wa1,
  input           i_wa1_usr,
  input   [31:0]  i_d1
);

reg [31:0] r00_usr;
reg [31:0] r01_usr;
reg [31:0] r02_usr;
reg [31:0] r03_usr;
reg [31:0] r04_usr;
reg [31:0] r05_usr;
reg [31:0] r06_usr;
reg [31:0] r07_usr;
reg [31:0] r08_usr;
reg [31:0] r09_usr;
reg [31:0] r10_usr;
reg [31:0] r11_usr;
reg [31:0] r12_usr;
reg [31:0] r13_usr;
reg [31:0] r14_usr;
reg [31:0] r13_svc;
reg [31:0] r14_svc;
reg [31:0] r13_abt;
reg [31:0] r14_abt;
reg [31:0] r13_und;
reg [31:0] r14_und;
reg [31:0] r13_irq;
reg [31:0] r14_irq;
reg [31:0] r08_fiq;
reg [31:0] r09_fiq;
reg [31:0] r10_fiq;
reg [31:0] r11_fiq;
reg [31:0] r12_fiq;
reg [31:0] r13_fiq;
reg [31:0] r14_fiq;

wire usrbank;
wire fiqbank;
wire irqbank;
wire svcbank;
wire abtbank;
wire undbank;

wire usrbank_exc;
wire fiqbank_exc;
wire irqbank_exc;
wire svcbank_exc;
wire abtbank_exc;
wire undbank_exc;

mode_decoder u_mode_decoder_noexc(
  .i_mode(i_mode),
  .o_usrbank(usrbank),
  .o_fiqbank(fiqbank),
  .o_irqbank(irqbank),
  .o_svcbank(svcbank),
  .o_abtbank(abtbank),
  .o_undbank(undbank)
);

mode_decoder u_mode_decoder_exc(
  .i_mode(i_wa0_mode_exc),
  .o_usrbank(usrbank_exc),
  .o_fiqbank(fiqbank_exc),
  .o_irqbank(irqbank_exc),
  .o_svcbank(svcbank_exc),
  .o_abtbank(abtbank_exc),
  .o_undbank(undbank_exc)
);

wire usrbank_rd =  i_rd_sel_usr | usrbank ;
wire fiqbank_rd = ~i_rd_sel_usr & fiqbank ;
wire irqbank_rd = ~i_rd_sel_usr & irqbank ;
wire svcbank_rd = ~i_rd_sel_usr & svcbank ;
wire abtbank_rd = ~i_rd_sel_usr & abtbank ;
wire undbank_rd = ~i_rd_sel_usr & undbank ;

wire usrbank_wa0 = i_wa0_exc ? usrbank_exc : usrbank ;
wire fiqbank_wa0 = i_wa0_exc ? fiqbank_exc : fiqbank ;
wire irqbank_wa0 = i_wa0_exc ? irqbank_exc : irqbank ;
wire svcbank_wa0 = i_wa0_exc ? svcbank_exc : svcbank ;
wire abtbank_wa0 = i_wa0_exc ? abtbank_exc : abtbank ;
wire undbank_wa0 = i_wa0_exc ? undbank_exc : undbank ;

wire usrbank_wa1 =  i_wa1_usr | usrbank ;
wire fiqbank_wa1 = ~i_wa1_usr & fiqbank ;
wire irqbank_wa1 = ~i_wa1_usr & irqbank ;
wire svcbank_wa1 = ~i_wa1_usr & svcbank ;
wire abtbank_wa1 = ~i_wa1_usr & abtbank ;
wire undbank_wa1 = ~i_wa1_usr & undbank ;

wire we0_r00_usr = i_we0 & i_wa0 ==  0                  ;
wire we0_r01_usr = i_we0 & i_wa0 ==  1                  ;
wire we0_r02_usr = i_we0 & i_wa0 ==  2                  ;
wire we0_r03_usr = i_we0 & i_wa0 ==  3                  ;
wire we0_r04_usr = i_we0 & i_wa0 ==  4                  ;
wire we0_r05_usr = i_we0 & i_wa0 ==  5                  ;
wire we0_r06_usr = i_we0 & i_wa0 ==  6                  ;
wire we0_r07_usr = i_we0 & i_wa0 ==  7                  ;
wire we0_r08_usr = i_we0 & i_wa0 ==  8 & ~fiqbank_wa0 ;
wire we0_r09_usr = i_we0 & i_wa0 ==  9 & ~fiqbank_wa0 ;
wire we0_r10_usr = i_we0 & i_wa0 == 10 & ~fiqbank_wa0 ;
wire we0_r11_usr = i_we0 & i_wa0 == 11 & ~fiqbank_wa0 ;
wire we0_r12_usr = i_we0 & i_wa0 == 12 & ~fiqbank_wa0 ;
wire we0_r13_usr = i_we0 & i_wa0 == 13 &  usrbank_wa0 ;
wire we0_r14_usr = i_we0 & i_wa0 == 14 &  usrbank_wa0 ;
wire we0_r13_svc = i_we0 & i_wa0 == 13 &  svcbank_wa0 ;
wire we0_r14_svc = i_we0 & i_wa0 == 14 &  svcbank_wa0 ;
wire we0_r13_abt = i_we0 & i_wa0 == 13 &  abtbank_wa0 ;
wire we0_r14_abt = i_we0 & i_wa0 == 14 &  abtbank_wa0 ;
wire we0_r13_und = i_we0 & i_wa0 == 13 &  undbank_wa0 ;
wire we0_r14_und = i_we0 & i_wa0 == 14 &  undbank_wa0 ;
wire we0_r13_irq = i_we0 & i_wa0 == 13 &  irqbank_wa0 ;
wire we0_r14_irq = i_we0 & i_wa0 == 14 &  irqbank_wa0 ;
wire we0_r08_fiq = i_we0 & i_wa0 ==  8 &  fiqbank_wa0 ;
wire we0_r09_fiq = i_we0 & i_wa0 ==  9 &  fiqbank_wa0 ;
wire we0_r10_fiq = i_we0 & i_wa0 == 10 &  fiqbank_wa0 ;
wire we0_r11_fiq = i_we0 & i_wa0 == 11 &  fiqbank_wa0 ;
wire we0_r12_fiq = i_we0 & i_wa0 == 12 &  fiqbank_wa0 ;
wire we0_r13_fiq = i_we0 & i_wa0 == 13 &  fiqbank_wa0 ;
wire we0_r14_fiq = i_we0 & i_wa0 == 14 &  fiqbank_wa0 ;

wire we1_r00_usr = i_we1 & i_wa1 ==  0                  ;
wire we1_r01_usr = i_we1 & i_wa1 ==  1                  ;
wire we1_r02_usr = i_we1 & i_wa1 ==  2                  ;
wire we1_r03_usr = i_we1 & i_wa1 ==  3                  ;
wire we1_r04_usr = i_we1 & i_wa1 ==  4                  ;
wire we1_r05_usr = i_we1 & i_wa1 ==  5                  ;
wire we1_r06_usr = i_we1 & i_wa1 ==  6                  ;
wire we1_r07_usr = i_we1 & i_wa1 ==  7                  ;
wire we1_r08_usr = i_we1 & i_wa1 ==  8 & ~fiqbank_wa1 ;
wire we1_r09_usr = i_we1 & i_wa1 ==  9 & ~fiqbank_wa1 ;
wire we1_r10_usr = i_we1 & i_wa1 == 10 & ~fiqbank_wa1 ;
wire we1_r11_usr = i_we1 & i_wa1 == 11 & ~fiqbank_wa1 ;
wire we1_r12_usr = i_we1 & i_wa1 == 12 & ~fiqbank_wa1 ;
wire we1_r13_usr = i_we1 & i_wa1 == 13 &  usrbank_wa1 ;
wire we1_r14_usr = i_we1 & i_wa1 == 14 &  usrbank_wa1 ;
wire we1_r13_svc = i_we1 & i_wa1 == 13 &  svcbank_wa1 ;
wire we1_r14_svc = i_we1 & i_wa1 == 14 &  svcbank_wa1 ;
wire we1_r13_abt = i_we1 & i_wa1 == 13 &  abtbank_wa1 ;
wire we1_r14_abt = i_we1 & i_wa1 == 14 &  abtbank_wa1 ;
wire we1_r13_und = i_we1 & i_wa1 == 13 &  undbank_wa1 ;
wire we1_r14_und = i_we1 & i_wa1 == 14 &  undbank_wa1 ;
wire we1_r13_irq = i_we1 & i_wa1 == 13 &  irqbank_wa1 ;
wire we1_r14_irq = i_we1 & i_wa1 == 14 &  irqbank_wa1 ;
wire we1_r08_fiq = i_we1 & i_wa1 ==  8 &  fiqbank_wa1 ;
wire we1_r09_fiq = i_we1 & i_wa1 ==  9 &  fiqbank_wa1 ;
wire we1_r10_fiq = i_we1 & i_wa1 == 10 &  fiqbank_wa1 ;
wire we1_r11_fiq = i_we1 & i_wa1 == 11 &  fiqbank_wa1 ;
wire we1_r12_fiq = i_we1 & i_wa1 == 12 &  fiqbank_wa1 ;
wire we1_r13_fiq = i_we1 & i_wa1 == 13 &  fiqbank_wa1 ;
wire we1_r14_fiq = i_we1 & i_wa1 == 14 &  fiqbank_wa1 ;

assign o_rn =
  {32{i_rn_sel ==  0           }} & r00_usr |
  {32{i_rn_sel ==  1           }} & r01_usr |
  {32{i_rn_sel ==  2           }} & r02_usr |
  {32{i_rn_sel ==  3           }} & r03_usr |
  {32{i_rn_sel ==  4           }} & r04_usr |
  {32{i_rn_sel ==  5           }} & r05_usr |
  {32{i_rn_sel ==  6           }} & r06_usr |
  {32{i_rn_sel ==  7           }} & r07_usr |
  {32{i_rn_sel ==  8 & ~fiqbank}} & r08_usr |
  {32{i_rn_sel ==  9 & ~fiqbank}} & r09_usr |
  {32{i_rn_sel == 10 & ~fiqbank}} & r10_usr |
  {32{i_rn_sel == 11 & ~fiqbank}} & r11_usr |
  {32{i_rn_sel == 12 & ~fiqbank}} & r12_usr |
  {32{i_rn_sel == 13 &  usrbank}} & r13_usr |
  {32{i_rn_sel == 14 &  usrbank}} & r14_usr |
  {32{i_rn_sel == 13 &  svcbank}} & r13_svc |
  {32{i_rn_sel == 14 &  svcbank}} & r14_svc |
  {32{i_rn_sel == 13 &  abtbank}} & r13_abt |
  {32{i_rn_sel == 14 &  abtbank}} & r14_abt |
  {32{i_rn_sel == 13 &  undbank}} & r13_und |
  {32{i_rn_sel == 14 &  undbank}} & r14_und |
  {32{i_rn_sel == 13 &  irqbank}} & r13_irq |
  {32{i_rn_sel == 14 &  irqbank}} & r14_irq |
  {32{i_rn_sel ==  8 &  fiqbank}} & r08_fiq |
  {32{i_rn_sel ==  9 &  fiqbank}} & r09_fiq |
  {32{i_rn_sel == 10 &  fiqbank}} & r10_fiq |
  {32{i_rn_sel == 11 &  fiqbank}} & r11_fiq |
  {32{i_rn_sel == 12 &  fiqbank}} & r12_fiq |
  {32{i_rn_sel == 13 &  fiqbank}} & r13_fiq |
  {32{i_rn_sel == 14 &  fiqbank}} & r14_fiq ;

assign o_rm =
  {32{i_rm_sel ==  0           }} & r00_usr |
  {32{i_rm_sel ==  1           }} & r01_usr |
  {32{i_rm_sel ==  2           }} & r02_usr |
  {32{i_rm_sel ==  3           }} & r03_usr |
  {32{i_rm_sel ==  4           }} & r04_usr |
  {32{i_rm_sel ==  5           }} & r05_usr |
  {32{i_rm_sel ==  6           }} & r06_usr |
  {32{i_rm_sel ==  7           }} & r07_usr |
  {32{i_rm_sel ==  8 & ~fiqbank}} & r08_usr |
  {32{i_rm_sel ==  9 & ~fiqbank}} & r09_usr |
  {32{i_rm_sel == 10 & ~fiqbank}} & r10_usr |
  {32{i_rm_sel == 11 & ~fiqbank}} & r11_usr |
  {32{i_rm_sel == 12 & ~fiqbank}} & r12_usr |
  {32{i_rm_sel == 13 &  usrbank}} & r13_usr |
  {32{i_rm_sel == 14 &  usrbank}} & r14_usr |
  {32{i_rm_sel == 13 &  svcbank}} & r13_svc |
  {32{i_rm_sel == 14 &  svcbank}} & r14_svc |
  {32{i_rm_sel == 13 &  abtbank}} & r13_abt |
  {32{i_rm_sel == 14 &  abtbank}} & r14_abt |
  {32{i_rm_sel == 13 &  undbank}} & r13_und |
  {32{i_rm_sel == 14 &  undbank}} & r14_und |
  {32{i_rm_sel == 13 &  irqbank}} & r13_irq |
  {32{i_rm_sel == 14 &  irqbank}} & r14_irq |
  {32{i_rm_sel ==  8 &  fiqbank}} & r08_fiq |
  {32{i_rm_sel ==  9 &  fiqbank}} & r09_fiq |
  {32{i_rm_sel == 10 &  fiqbank}} & r10_fiq |
  {32{i_rm_sel == 11 &  fiqbank}} & r11_fiq |
  {32{i_rm_sel == 12 &  fiqbank}} & r12_fiq |
  {32{i_rm_sel == 13 &  fiqbank}} & r13_fiq |
  {32{i_rm_sel == 14 &  fiqbank}} & r14_fiq ;

assign o_rs =
  {32{i_rs_sel ==  0           }} & r00_usr |
  {32{i_rs_sel ==  1           }} & r01_usr |
  {32{i_rs_sel ==  2           }} & r02_usr |
  {32{i_rs_sel ==  3           }} & r03_usr |
  {32{i_rs_sel ==  4           }} & r04_usr |
  {32{i_rs_sel ==  5           }} & r05_usr |
  {32{i_rs_sel ==  6           }} & r06_usr |
  {32{i_rs_sel ==  7           }} & r07_usr |
  {32{i_rs_sel ==  8 & ~fiqbank}} & r08_usr |
  {32{i_rs_sel ==  9 & ~fiqbank}} & r09_usr |
  {32{i_rs_sel == 10 & ~fiqbank}} & r10_usr |
  {32{i_rs_sel == 11 & ~fiqbank}} & r11_usr |
  {32{i_rs_sel == 12 & ~fiqbank}} & r12_usr |
  {32{i_rs_sel == 13 &  usrbank}} & r13_usr |
  {32{i_rs_sel == 14 &  usrbank}} & r14_usr |
  {32{i_rs_sel == 13 &  svcbank}} & r13_svc |
  {32{i_rs_sel == 14 &  svcbank}} & r14_svc |
  {32{i_rs_sel == 13 &  abtbank}} & r13_abt |
  {32{i_rs_sel == 14 &  abtbank}} & r14_abt |
  {32{i_rs_sel == 13 &  undbank}} & r13_und |
  {32{i_rs_sel == 14 &  undbank}} & r14_und |
  {32{i_rs_sel == 13 &  irqbank}} & r13_irq |
  {32{i_rs_sel == 14 &  irqbank}} & r14_irq |
  {32{i_rs_sel ==  8 &  fiqbank}} & r08_fiq |
  {32{i_rs_sel ==  9 &  fiqbank}} & r09_fiq |
  {32{i_rs_sel == 10 &  fiqbank}} & r10_fiq |
  {32{i_rs_sel == 11 &  fiqbank}} & r11_fiq |
  {32{i_rs_sel == 12 &  fiqbank}} & r12_fiq |
  {32{i_rs_sel == 13 &  fiqbank}} & r13_fiq |
  {32{i_rs_sel == 14 &  fiqbank}} & r14_fiq ;

assign o_rd =
  {32{i_rd_sel ==  0              }} & r00_usr |
  {32{i_rd_sel ==  1              }} & r01_usr |
  {32{i_rd_sel ==  2              }} & r02_usr |
  {32{i_rd_sel ==  3              }} & r03_usr |
  {32{i_rd_sel ==  4              }} & r04_usr |
  {32{i_rd_sel ==  5              }} & r05_usr |
  {32{i_rd_sel ==  6              }} & r06_usr |
  {32{i_rd_sel ==  7              }} & r07_usr |
  {32{i_rd_sel ==  8 & ~fiqbank_rd}} & r08_usr |
  {32{i_rd_sel ==  9 & ~fiqbank_rd}} & r09_usr |
  {32{i_rd_sel == 10 & ~fiqbank_rd}} & r10_usr |
  {32{i_rd_sel == 11 & ~fiqbank_rd}} & r11_usr |
  {32{i_rd_sel == 12 & ~fiqbank_rd}} & r12_usr |
  {32{i_rd_sel == 13 &  usrbank_rd}} & r13_usr |
  {32{i_rd_sel == 14 &  usrbank_rd}} & r14_usr |
  {32{i_rd_sel == 13 &  svcbank_rd}} & r13_svc |
  {32{i_rd_sel == 14 &  svcbank_rd}} & r14_svc |
  {32{i_rd_sel == 13 &  abtbank_rd}} & r13_abt |
  {32{i_rd_sel == 14 &  abtbank_rd}} & r14_abt |
  {32{i_rd_sel == 13 &  undbank_rd}} & r13_und |
  {32{i_rd_sel == 14 &  undbank_rd}} & r14_und |
  {32{i_rd_sel == 13 &  irqbank_rd}} & r13_irq |
  {32{i_rd_sel == 14 &  irqbank_rd}} & r14_irq |
  {32{i_rd_sel ==  8 &  fiqbank_rd}} & r08_fiq |
  {32{i_rd_sel ==  9 &  fiqbank_rd}} & r09_fiq |
  {32{i_rd_sel == 10 &  fiqbank_rd}} & r10_fiq |
  {32{i_rd_sel == 11 &  fiqbank_rd}} & r11_fiq |
  {32{i_rd_sel == 12 &  fiqbank_rd}} & r12_fiq |
  {32{i_rd_sel == 13 &  fiqbank_rd}} & r13_fiq |
  {32{i_rd_sel == 14 &  fiqbank_rd}} & r14_fiq ;

always @(posedge i_clk) begin
  if ( we0_r00_usr | we1_r00_usr ) r00_usr <= we0_r00_usr ? i_d0 : i_d1 ;
  if ( we0_r01_usr | we1_r01_usr ) r01_usr <= we0_r01_usr ? i_d0 : i_d1 ;
  if ( we0_r02_usr | we1_r02_usr ) r02_usr <= we0_r02_usr ? i_d0 : i_d1 ;
  if ( we0_r03_usr | we1_r03_usr ) r03_usr <= we0_r03_usr ? i_d0 : i_d1 ;
  if ( we0_r04_usr | we1_r04_usr ) r04_usr <= we0_r04_usr ? i_d0 : i_d1 ;
  if ( we0_r05_usr | we1_r05_usr ) r05_usr <= we0_r05_usr ? i_d0 : i_d1 ;
  if ( we0_r06_usr | we1_r06_usr ) r06_usr <= we0_r06_usr ? i_d0 : i_d1 ;
  if ( we0_r07_usr | we1_r07_usr ) r07_usr <= we0_r07_usr ? i_d0 : i_d1 ;
  if ( we0_r08_usr | we1_r08_usr ) r08_usr <= we0_r08_usr ? i_d0 : i_d1 ;
  if ( we0_r09_usr | we1_r09_usr ) r09_usr <= we0_r09_usr ? i_d0 : i_d1 ;
  if ( we0_r10_usr | we1_r10_usr ) r10_usr <= we0_r10_usr ? i_d0 : i_d1 ;
  if ( we0_r11_usr | we1_r11_usr ) r11_usr <= we0_r11_usr ? i_d0 : i_d1 ;
  if ( we0_r12_usr | we1_r12_usr ) r12_usr <= we0_r12_usr ? i_d0 : i_d1 ;
  if ( we0_r13_usr | we1_r13_usr ) r13_usr <= we0_r13_usr ? i_d0 : i_d1 ;
  if ( we0_r14_usr | we1_r14_usr ) r14_usr <= we0_r14_usr ? i_d0 : i_d1 ;
  if ( we0_r13_svc | we1_r13_svc ) r13_svc <= we0_r13_svc ? i_d0 : i_d1 ;
  if ( we0_r14_svc | we1_r14_svc ) r14_svc <= we0_r14_svc ? i_d0 : i_d1 ;
  if ( we0_r13_abt | we1_r13_abt ) r13_abt <= we0_r13_abt ? i_d0 : i_d1 ;
  if ( we0_r14_abt | we1_r14_abt ) r14_abt <= we0_r14_abt ? i_d0 : i_d1 ;
  if ( we0_r13_und | we1_r13_und ) r13_und <= we0_r13_und ? i_d0 : i_d1 ;
  if ( we0_r14_und | we1_r14_und ) r14_und <= we0_r14_und ? i_d0 : i_d1 ;
  if ( we0_r13_irq | we1_r13_irq ) r13_irq <= we0_r13_irq ? i_d0 : i_d1 ;
  if ( we0_r14_irq | we1_r14_irq ) r14_irq <= we0_r14_irq ? i_d0 : i_d1 ;
  if ( we0_r08_fiq | we1_r08_fiq ) r08_fiq <= we0_r08_fiq ? i_d0 : i_d1 ;
  if ( we0_r09_fiq | we1_r09_fiq ) r09_fiq <= we0_r09_fiq ? i_d0 : i_d1 ;
  if ( we0_r10_fiq | we1_r10_fiq ) r10_fiq <= we0_r10_fiq ? i_d0 : i_d1 ;
  if ( we0_r11_fiq | we1_r11_fiq ) r11_fiq <= we0_r11_fiq ? i_d0 : i_d1 ;
  if ( we0_r12_fiq | we1_r12_fiq ) r12_fiq <= we0_r12_fiq ? i_d0 : i_d1 ;
  if ( we0_r13_fiq | we1_r13_fiq ) r13_fiq <= we0_r13_fiq ? i_d0 : i_d1 ;
  if ( we0_r14_fiq | we1_r14_fiq ) r14_fiq <= we0_r14_fiq ? i_d0 : i_d1 ;
end

`ifndef SYNTHESIS

reg     trace;

initial trace = $test$plusargs("trace") != 0;

always @(posedge i_clk) begin
  if (trace) begin
    if ( we0_r00_usr | we1_r00_usr ) $display("$r00_usr=%x", we0_r00_usr ? i_d0 : i_d1);
    if ( we0_r01_usr | we1_r01_usr ) $display("$r01_usr=%x", we0_r01_usr ? i_d0 : i_d1);
    if ( we0_r02_usr | we1_r02_usr ) $display("$r02_usr=%x", we0_r02_usr ? i_d0 : i_d1);
    if ( we0_r03_usr | we1_r03_usr ) $display("$r03_usr=%x", we0_r03_usr ? i_d0 : i_d1);
    if ( we0_r04_usr | we1_r04_usr ) $display("$r04_usr=%x", we0_r04_usr ? i_d0 : i_d1);
    if ( we0_r05_usr | we1_r05_usr ) $display("$r05_usr=%x", we0_r05_usr ? i_d0 : i_d1);
    if ( we0_r06_usr | we1_r06_usr ) $display("$r06_usr=%x", we0_r06_usr ? i_d0 : i_d1);
    if ( we0_r07_usr | we1_r07_usr ) $display("$r07_usr=%x", we0_r07_usr ? i_d0 : i_d1);
    if ( we0_r08_usr | we1_r08_usr ) $display("$r08_usr=%x", we0_r08_usr ? i_d0 : i_d1);
    if ( we0_r09_usr | we1_r09_usr ) $display("$r09_usr=%x", we0_r09_usr ? i_d0 : i_d1);
    if ( we0_r10_usr | we1_r10_usr ) $display("$r10_usr=%x", we0_r10_usr ? i_d0 : i_d1);
    if ( we0_r11_usr | we1_r11_usr ) $display("$r11_usr=%x", we0_r11_usr ? i_d0 : i_d1);
    if ( we0_r12_usr | we1_r12_usr ) $display("$r12_usr=%x", we0_r12_usr ? i_d0 : i_d1);
    if ( we0_r13_usr | we1_r13_usr ) $display("$r13_usr=%x", we0_r13_usr ? i_d0 : i_d1);
    if ( we0_r14_usr | we1_r14_usr ) $display("$r14_usr=%x", we0_r14_usr ? i_d0 : i_d1);
    if ( we0_r13_svc | we1_r13_svc ) $display("$r13_svc=%x", we0_r13_svc ? i_d0 : i_d1);
    if ( we0_r14_svc | we1_r14_svc ) $display("$r14_svc=%x", we0_r14_svc ? i_d0 : i_d1);
    if ( we0_r13_abt | we1_r13_abt ) $display("$r13_abt=%x", we0_r13_abt ? i_d0 : i_d1);
    if ( we0_r14_abt | we1_r14_abt ) $display("$r14_abt=%x", we0_r14_abt ? i_d0 : i_d1);
    if ( we0_r13_und | we1_r13_und ) $display("$r13_und=%x", we0_r13_und ? i_d0 : i_d1);
    if ( we0_r14_und | we1_r14_und ) $display("$r14_und=%x", we0_r14_und ? i_d0 : i_d1);
    if ( we0_r13_irq | we1_r13_irq ) $display("$r13_irq=%x", we0_r13_irq ? i_d0 : i_d1);
    if ( we0_r14_irq | we1_r14_irq ) $display("$r14_irq=%x", we0_r14_irq ? i_d0 : i_d1);
    if ( we0_r08_fiq | we1_r08_fiq ) $display("$r08_fiq=%x", we0_r08_fiq ? i_d0 : i_d1);
    if ( we0_r09_fiq | we1_r09_fiq ) $display("$r09_fiq=%x", we0_r09_fiq ? i_d0 : i_d1);
    if ( we0_r10_fiq | we1_r10_fiq ) $display("$r10_fiq=%x", we0_r10_fiq ? i_d0 : i_d1);
    if ( we0_r11_fiq | we1_r11_fiq ) $display("$r11_fiq=%x", we0_r11_fiq ? i_d0 : i_d1);
    if ( we0_r12_fiq | we1_r12_fiq ) $display("$r12_fiq=%x", we0_r12_fiq ? i_d0 : i_d1);
    if ( we0_r13_fiq | we1_r13_fiq ) $display("$r13_fiq=%x", we0_r13_fiq ? i_d0 : i_d1);
    if ( we0_r14_fiq | we1_r14_fiq ) $display("$r14_fiq=%x", we0_r14_fiq ? i_d0 : i_d1);
  end
end

`endif

endmodule
